The present invention relates generally to memory devices and in particular to an architecture and method for controlling data transfers over an internal buffered bus for a DRAM.
In a computer system, the various subsystems interface and communicate with one another via a bus. There is typically a bus between the computer""s main memory and the processor, as well as a bus between the processor and the input/output (I/O) devices. Processor-memory buses are short, generally high speed and are matched to the memory system so as to maximize memory-processor bandwidth. I/O buses, by contrast, can be lengthy, and can have different types of devices in varying bandwidths connected to them.
Since the I/O bus usually transfers data to or from memory, the speed of the memory affects performance of the computer system. Usually, integrated memory circuits are slower in operation than the processor. This mismatch in memory access speed versus processor speed presents a problem, particularly since the computer system may have to wait a certain amount of time for each memory access operation. This problem is illustrated in real-time data acquisition systems, for example, where a data source outputs data at a high rate, valuable information might be lost if the receiving device is unable to process the information in an orderly fashion at the rate at which data is generated.
To reduce the time required to send data between a peripheral device and the memory circuit, a digital data buffer circuit, arranged as a First-in/First-out (FIFO) buffer may be used. The FIFO is normally connected external or separate from the memory circuits and compensates for the difference in communications speed by allowing the sending device to write or transmit data into the FIFO at its own rate without being interrupted by the receiving device. Nonetheless, memory access operations associated with transferring data into memory from the FIFO places restrictions upon the read and write operations of the peripheral device with respect to the internal read and write operations of the memory circuit.
With respect to the memory circuits of a computer system, dynamic random access memory modules (DRAMs) are typically utilized. DRAMs are desirable from a cost standpoint even though they are significantly slower than static random access memory modules (SRAMs).
DRAM memory cells are basically charge storage capacitors with access transistors. Due to the capacitance of DRAMs, DRAMs require more time than SRAMs to store or write data into their memory cells, and they require separate refresh circuitry to maintain the charge of each memory cell. Further, for packaging reasons, DRAMs use a multiplexed addressing structure where one-half the memory address, referred to as the row address, is provided in a first cycle and the remainder of the address, the column address, is provided in a second cycle. The use of the multiplexed addressing saves space but consumes time. Consequently, DRAMs require extra time to provided the row and column addresses, as well as extra time to store data in its internal memory cells corresponding to the address. DRAMs require an appreciable amount of set-up and cycle time which can hinder I/O performance. This significant amount of setup time reduces system performance since the system must insert wait states while the DRAM address is being established before allowing transfer of the data.
To increase I/O bus performance, there are a variety of techniques available. However, these techniques may adversely affect other performance metrics. For example, to obtain fast response time for I/O operations, the bus latency must be minimized by streamlining the communication path. On the other hand, to sustain high I/O data rates, the bus bandwidth must be maximized. The bus bandwidth can be increased by using more buffering and by communicating larger blocks of data, both of which increase the bus latency. Clearly these two goals, low latency and bus bandwidth, can lead to conflicting design requirements.
Thus, substantial performance increases in I/O bus performance could be realized if there were a means available which allowed a peripheral device to write data at a high speed while simultaneously allowing the memory to read the data as it is able to, thereby freeing up the peripheral device for other tasks much sooner than would otherwise be possible. Further, if internal read operations in a memory device could be prioritized over internal write operations in the same memory device, processor-memory bus performance likewise would be improved.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a computer system which utilizes FIFOs placed directly on a memory circuit to improve system performance in the exchange of data between a memory device and a microprocessor.
The above mentioned problems associated with improving computer system performance in the exchange of data between a microprocessor and a memory device are addressed by the present invention which will be understood by reading and studying the following specification.
The present invention describes the application of separate read and write FIFO buffers interfaced between an external connection of a memory device and with a memory array contained within the memory device. The use of FIFOs compensate for mismatches in communications speed that may exist between the microprocessor and the memory array. The use of separate read and write FIFOs permit decoupling of internal memory operations with external read and write operations such that internal and external operations are independently performed. Decoupling of internal memory operations with external reads and writes also permits prioritization of read and write commands such that if the memory device has both a read and a write command to execute, the write will be delayed in execution while the read is performed.
In particular, the present invention is a memory device comprising a memory array having a plurality of array banks, an internal communications bus coupled to the plurality of array banks, an external connection for coupling to an external bus, and input and output first-in first-out (FIFO) buffers located between the external connection and the internal communication bus for decoupling internal memory operations from external operations such that the internal and external operations are independently performed.
An embodiment of the present invention is a dynamic random access memory (DRAM). The memory device further comprising a controller that prioritizes internal read and write operations such that if the memory device has both a read and a write command to execute, the write will be delayed in execution while the read is performed. Two alternative embodiments would allow prioritizing write commands above read commands or would allow an external device such as the microprocessor to set the relative priorities of individual read and write commands. Also, the internal communications bus has a bus width wider than the external bus and operates at a slower frequency than the external bus.
The memory device further comprising a multiplexer located between the FIFO buffers and the external connection for interfacing the external bus having a bus width and a speed different than a bus width and a speed of the internal communications bus.
In another illustrative embodiment, the present invention is a processing system comprising a microprocessor, and a memory device coupled to the microprocessor via control and data lines, wherein the memory device further comprising a memory array and input and output first-in first-out (FIFO) buffers located between the data lines and the memory array for decoupling internal memory operations from external read and write operations such that the internal and external operations are independently performed.
In a further embodiment of the invention, a method of exchanging data between a microprocessor and a memory device comprising the steps of transmitting and receiving data via an external connection of the memory device, buffering data in input and output first-in first-out (FIFO) buffers located between the external connection and an internal communications bus, and reading and writing data to a plurality of memory array banks coupled to the internal communications bus such that internal memory operations are independently performed from external operations.
In a still further embodiment, the present invention is a memory device comprising a memory array having a plurality of array banks, an internal communications bus coupled to the plurality of array banks, an external connection for coupling to an external data lines, an input path located between the external data lines and the memory array comprising a demultiplexer and a write first-in first-out (FIFO) buffer coupled to the demultiplexer for decoupling internal write operations from external read and write operations such that the internal write and external memory operations are independently performed, an output path located between the memory array and the external data lines comprising a multiplexer and a read first-in first-out (FIFO) buffer coupled to the multiplexer for decoupling internal read operations from external read and write operations such that the internal read and external memory operations are independently performed, and a controller coupled to the multiplexers for prioritizing internal read and write operations such that if the memory device has both a read and a write command to execute, the write will be delayed in execution while the read is performed.
Still further embodiments would allow prioritizing write commands above read commands or would allow an external device, such as a microprocessor, to set the priority of individual or groups of read and write commands. Furthermore, the controller controls the multiplexers for data width such that the external data lines have a speed and a bus width different than a bus width and a speed of the internal communications bus.